Publication


Jungsook Yang; Chuny Chun; Bagherzadeh, N.; Seung Eun Lee; , "Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform," Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on , vol., no., pp.439-446, 9-11 Feb. 2011 (link)

Chifeng Wang; Wen-Hsiang Hu; Bagherzadeh, N.; , "A Wireless Network-on-Chip Design for Multicore Platforms," Parallel, Distributed and Network-Based Processing (PDP), 2011 19th Euromicro International Conference on , vol., no., pp.409-416, 9-11 Feb. 2011 (link)

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh, Area and Power-efficient Innovative Congestion-aware Network-on-Chip Architecture, Journal of Systems Architecture, Volume 57, Issue 1, Special Issue On-Chip Parallel And Network-Based Systems, January 2011, Pages 24-38 (link)

Chifeng Wang; Wen-Hsiang Hu; Bagherzadeh, N.; , "Congestion-aware Network-on-Chip Router Architecture," Computer Architecture and Digital Systems (CADS), 2010 15th CSI International Symposium on , vol., no., pp.137-144, 23-24 Sept. 2010 (link)

Frank Penczek, Stephan Herhut, Sven-Bodo Scholz, Alex Shafarenko, JungSook Yang, Chun-Yi Chen, Nader Bagherzadeh, Clemens Grelck, "Message Driven Programming with S-Net: Methodology and Performance," icppw, pp.405-412, 2010 39th International Conference on Parallel Processing Workshops, 2010 (link)

Chifeng Wang; Wen-Hsiang Hu; Bagherzadeh, N.; Seung Eun Lee; , "Area and Power-efficient Innovative Network-on-Chip Architecture," Parallel, Distributed and Network-Based Processing (PDP), 2010 18th Euromicro International Conference on , vol., no., pp.533-539, 17-19 Feb. 2010 (link)

Alhussien, A.; Chifeng Wang; Bagherzadeh, N.; , "A scalable delay insensitive asynchronous NoC with adaptive routing," Telecommunications (ICT), 2010 IEEE 17th International Conference on , vol., no., pp.995-1002, 4-7 April 2010 (link)

Wen-Hsiang Hu; Jun Ho Bahn; Bagherzadeh, N.; , "Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform," Computer Architecture and High Performance Computing, 2009. SBAC-PAD '09. 21st International Symposium on , vol., no., pp.35-40, 28-31 Oct. 2009 (link)

Faruk Bagci, Theo Ungerer, Nader Bagherzadeh, "SecSens - Security Architecture for Wireless Sensor Networks," sensorcomm, pp.449-454, 2009 Third International Conference on Sensor Technologies and Applications, 2009 (link)

Seung Eun Lee; Wilkerson, C.; Ming Zhang; Yavatkar, R.; Shih-Lien Lu; Bagherzadeh, N.; , "Low power adaptive pipeline based on instruction isolation," Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design , vol., no., pp.788-793, 16-18 March 2009 (link)

Seung Eun LEE and Nader Bagherzadeh, "A Variable Frequency Link for a Power-Aware Network-on-Chip (NoC), " Integration, the VLSI Journal, Elsevier. 2009 (PDF)

Seung Eun LEE and Nader Bagherzadeh, "A High-level Power Model for Network-on-Chip (NoC) Router, " Computer & Electrical Engineering, Elsevier. 2009 (PDF)

Seung Eun Lee and Nader Bagherzadeh, "Clock Boosting Router: Increasing the Performance of an Adaptive Router in Network-on-Chip (NoC)", Scientia Iranica, Vol. 15, No. 6, pp. 579-588, December 2008.

Wen-Hsiang Hu, Seugn Eun Lee, and Nader Bagherzadeh, "DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture", NoCArc, First International Workshop on Network on Chip Architectures to be held in conjunction with MICRO-41, 2008. (PDF)

Jun Ho Bahn and Nader Bagherzadeh, "A Generic Traffic Model for On-Chip Interconnection Networks", NoCArc, First International Workshop on Network on Chip Architectures to be held in conjunction with MICRO-41, 2008. (PDF)

Wolfgang Trumler, Sebastian Schlingmann, Theo Ungerer, Jun Ho Bahn and Nader Bagherzadeh, "Self-optimized Routing in a Network-on-a-Chip," 20th IFIP World Computer Congress, Milano, Italy 7-10 September 2008. (PDF) (RIS)

Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh, "Parallel FFT Algorithms on Network-on-Chips," 5th International Conference on Information Technology : New Generations (ITNG 2008) (PDF) (BIB)

Nader Bagherzadeh and Masaru Matsuura, "Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip," 5th International Conference on Information Technology : New Generations (ITNG 2008) (BIB)

Jun Ho Bahn, Nader Bagherzadeh, "Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip(NoC) Architecture," 13th International CSI Computer Conference (CSICC 2008) (PDF)

Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, and Nader Bagherzadeh, "A Generic Networ Interface Architecture for an NoC based Multiprocessor SoC," International Symposium on Architecture of Computing System(ARCS2008), Lecture Notes in Computer Science, vol.4934, pp.247-260, Feb.2008. (PDF) (BIB)

Jun Ho Bahn, Seung Eun LEE, Yoon seok Yang, Jungsook Yang, and Nader Bagherzadeh, "Multi-Processor System Platform using Network-on-Chip (NoC) Techniques, " appears in Parallel Processing Letters. (PDF) (BIB)

Jun-Ho Bahn, Seung Eun LEE, and Nader Bagherzadeh, "Design of a router for network-on-chip, " International Journal of High Performance Systems Architecture 2007 - Vol. 1, No.2 pp. 98 - 105. (PDF)

Seung Eun Lee, Jun Ho Bahn and Nader Bagherzadeh, "Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)," Proceedings of the 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), Oct. 2007 (PDF)
(BIB)

Akira Hatanaka , Nader Bagherzadeh, "A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template,"
Proceedings of the 21st International Parallel and Distributed Processing Symposium, IPDPS 2007. (PDF)


Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh, "Design and Analysis of a Feasible Network-on-Chip(NoC) Architecture,"
in the Proc. of ITNG 2007.(PDF) (BIB)


Nozar Tabrizi, Nader Bagherzadeh, "A Parallel Sort Engine With Dynamic Memory For a Multiprocessor-on-a-Chip, "
Proceedings of the Fourth IASTED International Conference, Circuits,Signals,and Systems ,Nov.2006 (PDF)


Seung-Eun LEE, Nader Bagherzadeh, "Increasing the Throughput of an Adaptive Router in Network-on-Chip(NoC), "
in the Proc. of 3rd Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2006. (PDF)


Nozar Tabrizi, Nader Bagherzadeh, Amir H. Kamalizad and Haitao Du, "MaRS: A Macro-pipelined Reconfigurable System"
in the Proc. of the 1st conference on Computing frontiers, 2004. (PDF)

Invited Talks


"NePA: Multi-Processor System Platform Using a New Generation of Network-on-Chip Technique",
IFIP WG 10.3 Workshop, June 2007.

"Network-on-a-Chip (NoC): An Alternative Approach for the Design of Next Generation System-on-a-Chip (SoC)",
High Performance Computing Group Seminar, HiPEAC Web Seminar, Apr. 2007

"Design and Analysis of an Network-on-Chip (NoC) processor Arichtecture",
4th International System-on-Chip (SoC) Conference & Exhibit, Nov. 2006, Newport Beach, CA

Posters


Seung Eun LEE and Nader Bagherzadeh, "A Power-Aware Interconnection Network for a Multi-Processor SoC,"
in the Student Poster Session of the 6th Annual Industry Research Symposium, may. 2007

Seung-Eun LEE, Jun-Ho Bahn and Nader Bagherzadeh, "Design of An Adaptive Router Architecture for Network-on-Chip, "
in the Student Poster Session of the 5th Annual Industry Research Symposium, May. 2006. (PDF)

Patents


A Variable Frequency Link for an Interconnection Network, 2007, USA.
Clock Boosting Mechanism for an Adaptive Wormhole Router, 2006, USA.

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