Research Papers

Table of Contents

• VLIW Integer ProcEssoR (VIPER)
• Superscalar Design - Superscalar Digital Signal Processor (SDSP)
• Superscalar Architecture
• Multithreading
• Star Graphs
• Star-Connected Cycles Interconnection Networks
• Image Processing
• ATM

VLIW Integer ProcEssoR (VIPER)

• Arthur Abnous and Nader Bagherzadeh, Architectural Design and Analysis of a VLIW Processor.
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• Jeffrey Gray, Andrew Naylor, Arthur Abnous, and Nader Bagherzadeh, VIPER: A VLIW Integer Microprocessor.
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Superscalar Design - Superscalar Digital Signal Processor (SDSP)

• S. Wallace, N. Dagli, and N. Bagherzadeh, Design and Implementation of a Scheduling Unit for a Superscalar Microprocessor, submitted to IEEE Transactions on VLSI Design in March 1995.

• S. Wallace, N. Dagli, and N. Bagherzadeh, Design and Implementation of a 100 MHz Centralized Instruction Window for a Supe rscaler Microprocessor, 1995 International Conference on Computer Design, October 1995.
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• Nirav Dagli, Design and Implementation of a Scheduling Unit for a Superscalar Processor, Master's thesis, UCI, December 1994.
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• S. Wallace, N. Dagli, and N. Bagherzadeh, Design and Implementation of a 100MHz Reorder Buffer, 37th Midwest Symposium on Circuit and Systems, August 1994.
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• J. Lenell, S. Wallace, and N. Bagherzadeh, A 20 MHz CMOS Reorder Buffer for a Superscalar Microprocessor, 4th NASA Symposium on VLSI Design, October 1992.
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Superscalar Architecture

• S. Wallace and N. Bagherzadeh, Multiple Branch and Block Prediction, Third International Symposium on High-Performance Computer Architecture, February 1997.
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• S. Wallace and N. Bagherzadeh, A Scalable Register File Architecture for Dynamically Scheduled Processors, Parallel Architectures and Compilation Techniques '96, October 1996.
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• S. Wallace and N. Bagherzadeh, Instruction Fetching Mechanisms for Superscalar Microprocessors, Euro-Par '96, August 1996.
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• S. Wallace and N. Bagherzadeh, Performance Issues of a Superscalar Microprocessor, Microprocessors and Microsystems, May 1995.

• S. Wallace and N. Bagherzadeh, Performance Issues of a Superscalar Microprocessor, 23rd International Conference of Parallel Processing, August 1994.
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• S. Wallace, Performance Analysis of a Superscalar Architechture, Master's thesis, UCI, September 1993. *NOTE* ftp simulator from sdsp.ece.uci.edu NOT ece.uci.edu
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Multithreading

• Mark Pontius, Performance Enhancement of Desktop Multimedia with Multithreaded Extensions to a General Purpose Superscalar Microprocessor, MS Thesis, UCI, December 1998. (Also available as HTML)
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• Mat Loikkanen and Nader Bagherzadeh, A Fine-Grain Multithreading Superscalar Architecture, Parallel Architectures and Compilation Techniques '96, October 1996.
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• Manu Gulati and Nader Bagherzadeh, Performance Study of a Multithreaded Superscalar Microprocessor, 2nd International Symposium on High-Performance Computer Architecture, San Jose, California, February 1996, pp 291-301.
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• Manu Gulati, Multithreading on a Superscalar Processor, Master's thesis, UCI, December 1994.
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing, Proceedings of the 2nd International Euro-Par Conference, Vol. I, Lyon, France, August 26-29, 1996. Lecture Notes in Computer Science No. 1123, Springer-Verlag, pp. 247-252.
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing, Department of Electrical and Computer Engineering, University of California, Irvine, Technical Report ECE 96-05-01, May 1996.
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• M. M. de Azevedo, S. Latifi, and N. Bagherzadeh, Low Expansion Packings and Embeddings of Hypercubes into Star Graphs, Proceedings of the IEEE 15th Annual International Phoenix Conference on Computers and Communications, Phoenix, Arizona, March 27-29, 1996, pp. 115-122.
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• M. M. de Azevedo, S. Latifi, and N. Bagherzadeh, On Packing and Embedding Hypercubes into Star Graphs, Proceedings of the VI Brazilian Symposium on Computer Architecture and High Performance Computing (VI SBAC-PAD), Caxambu, Minas Gerais, Brazil, August 1-5, 1994, pp. 3-19.
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Space- and Time-Efficient Packings and Embeddings of Hypercubes into Star Graphs, Department of Electrical and Computer Engineering, University of California, Irvine, Technical Report ECE 94-11-01, November 1994.
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Star-Connected Cycles Interconnection Networks

• M. M. de Azevedo, N. Bagherzadeh, M. Dowd, and S. Latifi, Average Distance and Routing Algorithms in the Star-Connected Cycles Interconnection Network, Proceedings of the 8th IEEE Symposium on Parallel and Distributed Processing, New Orleans, Louisiana, October 23-26, 1996, pp. 443-452. (Note: use ghostview v. 1.5 or higher to view this file.).
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• M. M. de Azevedo, N. Bagherzadeh, Martin Dowd, and S. Latifi, Some Topological Properties of Star Connected Cycles, Information Processing Letters 58 (1996) 81-85.
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• M. M. de Azevedo, N. Bagherzadeh, M. Dowd, and S. Latifi, Average Distance and Routing Algorithms in the Star-Connected Cycles Interconnection Network, Department of Electrical and Computer Engineering, University of California, Irvine, Technical Report ECE 96-04-01, April 1996. (Note: use ghostview v. 1.5 or higher to view this file.).
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Embedding Meshes in the Star-Connected Cycles Interconnection Network. Presented at the 10th International Conference on Mathematical and Computer Modelling and Scientific Computing, Boston, Massachusetts, July 5-8, 1995. To appear in Mathematical Modelling and Scientific Computing. (Notes: 1) prints on A4 size paper, and 2) this postscript file is configured for manual paper feed.)
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Embedding Meshes in the Star-Connected Cycles Interconnection Network, Department of Electrical and Computer Engineering, University of California, Irvine, Technical Report ECE 95-10-01, October 1995.
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network, Journal of Parallel and Distributed Computing, 25, 209-222 (1995).
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• S. Latifi, M. M. de Azevedo, and N. Bagherzadeh, A Star-Based I/O-Bounded Network for Massively Parallel Systems, IEE Proceedings - Computers and Digital Techniques, Vol. 142, No. 1, January 1995, pp. 5-14.
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, Fault-Diameter of the Star-Connected Cycles Interconnection Network, Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), Vol. II (Software Technology), Maui, Hawaii, January 3-6, 1995, pp. 469-478.
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• S. Latifi, M. M. de Azevedo, and N. Bagherzadeh The Star Connected Cycles: A Fixed-Degree Interconnection Network for Parallel Processing, Proceedings of the 22nd International Conference on Parallel Processing, St. Charles, Illinois, August 16-20, 1993, Vol. 1, pp. 91-95.
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• M. M. de Azevedo, N. Bagherzadeh, and S. Latifi, The Star-Connected Cycles: A Fixed-Degree Interconnection Network for Massively Parallel Systems, Department of Electrical and Computer Engineering, University of California, Irvine, Technical Report ECE 93-02, March 1993.
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• S. Shoari and N. Bagherzadeh, Computation of Fast Fourier Transform on the Star-Connected Cycle Networks, Computers & Electrical Engineering, Vol22 N4:235-246, July 1996.
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• S. Shoari, N. Bagherzadeh, T.E. Milner, and J.S. Nelson, Moment Algorithms for Blood Vessel Detection in Infrared Images of Laser-Heated Skin, Computers & Electrical Engineering, Vol 23, N5, January 1998.
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• S. Shoari, N. Bagherzadeh, D. Goodman, T.E. Milner, D.J. Smithies, and J.S. Nelson, Parallel Algorithm for Pulsed Laser Infrared Tomography, The Seventh Annual Meeting of the American Society for Laser Medicine and Surgery, Inc., April 1997.

• A. Kavianpour, N. Bagherzadeh, S. Shoari, Finding Elliptical Shapes in an Image using a Pyramid Architecture, Computers & Electrical Engineering, Vol 21, N1:69-75, January 1995.
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• S. Shoari, A.Kavianpour, N. Bagherzadeh, Pyramid Simulation of Image Processing Applications, Image and Vision Computing, Vol 12, N8:523-9, October 1994.
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• A. Kavianpour, S. Shoari, N. Bagherzadeh, A New Approach for Circle Detection on Multiprocessors, Journal of Parallel and Distributed Computing, Vol 20, N2:256-60, February 1994.
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• F. Etemadi, M.S. Thesis: Design and Implementation of 155.52 Mbps ATM Transceiver.
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• H. K. Liu, M.S. Thesis: Efficient Structures For Digital Communications Systems.
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• N. Bagherzadeh, F. Kurdahi, F. Etemadi, H. K. Liu, Design and Implementation of a 52 Mbps ATM Transceiver.
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• F. Etemadi, Shaping Filter Design for a 155 Mbps 64-CAP ATM Transceiver.
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