Research

Michael Green’s group performs research in the area of analog/mixed-signal integrated circuit design, particularly with applications in high-speed broadband communications circuits.  His group has designed ICs, including SerDes, clock dividers, equalizers, and CDRs, demonstrating serial speeds of up to 40 Gb/s using standard 0.13 µm and 0.18 µm CMOS and BiCMOS fabrication processes.

Recent publications:


  1. X. Gui and M. M. Green, “Analysis of Nonlinearities in Injection-locked Frequency Dividers,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, Mar. 2015, pp. 945-953.

  2. M. A. Ganad, M. M. Green, and C. Dehollain, “A 15 μW 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB,” IEEE Transactions on Circuits and Systems - I, vol. 61, Dec. 2014, pp. 3321-3329.

  3. S. Huang, J. Cao, and M. M. Green, “An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS,” 2014 IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, CA, pp. 152-153.

  4. X. Gui and M. M. Green, “Design of CML Ring Oscillators with Low Supply Sensitivity,” IEEE Trans. on Circuits and Systems – I, vol. 60, July 2013, pp. 1753-1763.

  5. P. E. Thoppay, C. Dehollain, M. J. Declerq, and M. M. Green, “A 0.24nJ/bit Super-Regenerative Pulsed UWB receiver in 0.18μm CMOS,” IEEE J. of Solid-State Circuits, vol. 46, pp. 2623-2634, Nov. 2011.

 

Chip Gallery:

Novel high-speed clock divider topology for a clock divider using nonlinearities to achieve a wide frequency range (0.18 µm CMOS)

Designed by Dr. Xiaoyan Gui, presented at European Conf. on Circuit Theory & Design, August 2011.

40 Gb/s full-rate 2:1 MUX (0.18 µm CMOS).  This chip features a 40 GHz push-push VCO and a novel dynamic retimer.

Designed by Dr. Ahmad Yazdi, and published in IEEE Trans. on Microwave Theory and Techniques, vol. 59, Nov. 2011, pp. 2879-2887.

2.5 GHz VCO (0.18 µm CMOS) with reduced supply voltage sensitivity based on a negative-capacitance compensation circuit.

Designed by Dr. Xiaoyan Gui, presented at 2010 Custom Integrated Circuits Conf.   To appear in IEEE Trans. on Circuits and Systems.

40 Gb/s feedforward equalizer with 7 taps, T/2 spacing, 80 mW dissipation (65nm CMOS).

Designed by Dr. Afshin Momtaz, presented at ISSCC 2009 and published in IEEE J. of Solid-State Circuits, vol. 45, March 2010, pp. 629-639.

10 Gb/s decision feedback equalizer with 4 taps (0.13 µm CMOS).  This chip has been tested on a channel consisting of 300 m of multi-mode fiber in series with 12-inch FR4 trace.

Designed by Dr. Mahyar Karger, presented at ESSCIRC 2009.