Table of Contents
COMBINATIONAL LOGIC
Overview
Combinational vs. Sequential Logic
Static CMOS Circuit
Static CMOS
NMOS Transistors in Series/Parallel Connection
PMOS Transistors in Series/Parallel Connection
1’s, 0’s, and CMOS
Complementary CMOS Logic Style Construction (cont.)
Example Gate: NAND
NAND Gate Layout
Another NAND Layout
Example Gate: NOR
Example Gate: COMPLEX CMOS GATE
Construction of Complex Gates
Example Procedure
Bridge Networks
Dual Graphs and Networks
Systematic Gate Layout
Issues
4-input NAND Gate
Standard Cell Layout Methodology
Two Versions of (a+b).c
Graphs & Paths
Logic Graph
Consistent Euler Path
Layout Procedure
Example: x = ab+cd
Variations (1)
Variations (2)
Variations (3)
Properties of Complementary CMOS Gates
Properties of Complementary CMOS Gates
Transistor Sizing
Propagation Delay Analysis - The Switch Model
What is the Value of Ron?
Numerical Examples of Resistances for 1.2mm CMOS
Analysis of Propagation Delay
Design for Worst Case
Influence of Fan-In and Fan-Out on Delay
tp as a function of Fan-In
Fast Complex Gate - Design Techniques
Fast Complex Gate - Design Techniques (2)
Fast Complex Gate - Design Techniques (3)
Fast Complex Gate - Design Techniques (4)
Source & Drain Capacitances
Example: Full Adder
A Revised Adder Circuit
Ratioed Logic
Ratioed Logic
Active Loads
Load Lines of Ratioed Gates
Pseudo-NMOS
Pseudo-NMOS NAND Gate
Improved Loads
Improved Loads (2)
Example
Pass-Transistor Logic
NMOS-only switch
Solution 1: Transmission Gate
Resistance of Transmission Gate
Pass-Transistor Based Multiplexer
Transmission Gate XOR
Delay in Transmission Gate Networks
Elmore Delay (Chapter 8)
Delay Optimization
Transmission Gate Full Adder
(2) NMOS Only Logic: Level Restoring Transistor
Level Restoring Transistor
Solution 3: Single Transistor Pass Gate with VT=0
Complimentary Pass Transistor Logic
4 Input NAND in CPL
Dynamic Logic
Example
Transient Response
Dynamic 4 Input NAND Gate
Reliability Problems — Charge Leakage
Charge Sharing (redistribution)
Charge Redistribution - Solutions
Clock Feedthrough
Clock Feedthrough and Charge Sharing
Cascading Dynamic Gates
Domino Logic
Domino Logic - Characteristics
np-CMOS
np CMOS Adder
Manchester Carry Chain Adder
CMOS Circuit Styles - Summary
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